Forming through silicon vias (TSVs) in semiconductor devices may be challenging due to mechanical stress from etching trenches and filling the trenches with filler material. In addition, thermal stress may significantly reduce the reliability of the semiconductor device if the coefficient of thermal expansion (CTE) is different than the substrate material. The stress and the thermal expansions may limit the design and the process integration options in the production of semiconductor devices. In addition, voids in the filler material, electro migration and reduced conductivity may also cause a reduction in the performance of the semiconductor device. In addition, the costs of forming the TSVs may be high.